The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a vertical channel transistor in a semiconductor device.
As an integration degree of a semiconductor device increases, a transistor having smaller feature sizes is necessitated. For example, it is required that a transistor of a dynamic random access memory (DRAM) device has a device area of approximately 8F2 (F: minimum feature size) or less, preferably approximately 4F2. However, it is difficult to satisfy the required device area because of the present planar transistor structure in which a gate electrode is formed on a substrate, and junction regions are formed at both sides of the gate electrode. As a result, a vertical channel transistor structure has been proposed.
FIG. 1 illustrates a perspective view of a typical vertical channel transistor structure.
Referring to FIG. 1, a plurality of pillars P is formed on a substrate 10. The pillars P are formed of a substrate material and arranged in a first direction (X-X′) and a second direction (Y-Y′) crossing the first direction.
Buried bit lines 11 are formed in the substrate 10 between the respective pillars P arranged in the first direction. The buried bit lines 11 surround the pillars P and extend in the first direction. The buried bit lines 11 are isolated from each other by a device isolation trench T.
A surround type gate electrode (not shown) surrounding each of the pillars P is formed on an outer circumference of each pillar P. A word line 12, which is electrically connected to the surround type gate electrode and which extends in the second direction is formed on the outer circumference of the pillar P.
However, there is a limitation in a typical process for forming the buried bit line 11, resulting in an inferior device. Hereinafter, a typical method for fabricating the vertical channel transistor in the substrate and the limitation thereof will be described in detail with reference to FIGS. 2A and 2B.
FIGS. 2A and 2B illustrate a method for fabricating a typical vertical channel transistor in a semiconductor device and a limitation thereof. Particularly, FIGS. 2A and 2B illustrate cross-sectional views taken along line Y-Y′ of FIG. 1, i.e., the second direction.
Referring to FIG. 2A, a substrate structure which includes a substrate 20, a hard mask pattern 21, and a surround type gate electrode 22 is shown. The substrate 20 includes a plurality of pillars P arranged in a first direction and a second direction crossing the first direction. The hard mask pattern 21 is used to form the pillars P and is formed on each of the pillars P. The surround type gate electrode 22 surrounds a lower portion of each of the pillars P. Although not shown, a nitride layer is formed on a sidewall of the pillar P. The nitride layer serves as an etch barrier during a self-aligned contact (SAC) etching process for forming a following word line to protect the pillar P against an etching attack in a subsequent process.
Impurity ions are doped in the substrate 20 between the pillars P to form a bit line impurity region 23. An insulation layer 24 is deposited on a resulting structure, and the deposited insulation layer 24 is planarized until the hard mask pattern 21 is exposed.
Mask patterns 25 for forming a device isolation trench T are formed on the planarized resulting structure. The bit line impurity region 23 is divided by the device isolation trench T to form bit lines. The mask patterns 25 have a line-and-space pattern shape so that the substrate 20 between lines of the pillars P arranged in the first direction is exposed. A space width Ws between the mask patterns 25 is narrower than a space width WP between the lines of the pillars P arranged in the first direction by a predetermined amount.
Referring to FIG. 2B, the exposed insulation layer 24 and the substrate 20 formed below the insulation layer 24 are etched to a predetermined depth using the mask pattern 25 as an etch barrier to form the device isolation trench T extending in a direction parallel to the first direction in the substrate 20 between the lines of the pillars P arranged in the first direction. The device isolation trench T is formed with a depth penetrating the bit line impurity region 23 to form a buried bit line 23A surrounding the pillars P and extending in the first direction. A reference numeral 20A and a reference numeral 24A denote an etched substrate and an etched insulation layer after the etch process, respectively.
As semiconductor devices are highly integrated and patterns are micronizated, misalignment of the mask pattern 25 used to form the buried bit line 23A frequently occurs, resulting in unnecessary loss of the nitride layer formed on the sidewall of the pillar P in the etch process for forming the device isolation trench T (see FIG. 3). As a result, the pillar P is attacked in the subsequent process (for example, a word line forming process) due to such the loss of the nitride layer formed on the sidewall of the pillar P. Therefore, it is required to develop techniques capable of protecting the pillar P against the etching attack in the subsequent process even if the misalignment of the mask pattern 25 occurs.